
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
3
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Block Diagram - Register and PLL Logic Diagram (Positive Logic)
1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]
indicates all of the chip select outputs.
DA3..DA9,
DA10, DA12,
3
4
DA0..DA2, DBA2
DA3, DA4, DBA0, DBA1
Control Word
State Machine and
Control Logic
DCS[n:0]
DCKE0,
DODT0,
DCKE1
DODT1
PLL
R
D
Q
CE
R
D
Q
CE
R
D
Q
R
D
Q
R
D
Q
0
1
0
1
0
1
0
1
Pre-
Launch
CMR
Access
DA11,
DA13..DA15,
DBA0..DBA2
DRAS, DCAS,
DWE
Output
Inversion
4
A-Enable
B-Enable
Y0..Y3-
Enable
VREF
QxA3..QxA9,
QxA11,
QxA13..QxA15,
QxBA0..QxBA2
QxA10,
QxCAS,
QxWE
QxA12,
QxRAS,
QACKEn
QAODTn
QBCKEn
QBODTn
Y1
Y0
Y2
FBOUT
Y3
CK
FBIN
RESET
1/4 CK
delay
1/4 CK
delay
1/4 CK
delay
10K
~100K
OE0
OE1
OE2
OE3
1/4 CK
0
1
delay
QxCS[n:0]
DA0-DA2,
QxA0-QxA2,
DRAS
DCAS
DWE
(1)
CS
Logic